A CMOS-based mixed analog-logic standard cell product family

The authors focus on a description of the chip characteristics and design considerations regarding an experimental 40 K-equivalent gate CMOS-based analog-logic standard cell chip. The chip was developed to provide chip designers the capability to integrate structured analog functions with logic circuits without sacrificing performance, density, multiple part number capability, or testability. An overview of the CMOS-based processes is provided to aid in understanding the key analog design requirements. An overview of the design system and test methodology is provided for completeness. All elements of the successful CMOS standard cell chips were maintained and extended to include structured analog circuits for a variety of mixed analog-logic products