Thermal mitigation using thermal through silicon via (TTSV) in 3-D ICs

Thermal simulation of a stack consists of three IC layers bonded ¿face up¿ is performed using finite element modeling. Significant reduction of _~62°C in maximum chip temperature is predicted by inserting an electrically isolated thermal through silicon via (TTSV) having Cu core and oxide liner shell that extends across IC layers to the substrate. The effects of TTSV dimensions and its extension length in Si substrate are discussed. Additionally, the insertion of a thin layer of graphene at the interface between IC and ILD layers spreads heat more effectively to the TTSV and results in additional cooling.