Via design and scaling strategy for nanometer scale interconnect technologies

Via design and scaling is a critical issue for all nanometer scale interconnect technologies. This paper presents a comprehensive investigation into the robustness and accuracy of ITRS specified design guidelines for vias in nanometer scale technologies. Using rigorous thermal finite element simulations of 3-D via/line structures embedded in a chip, and material/geometrical data based on the ITRS, it is shown that design of vias based on ITRS specified maximum allowable currents for various technology nodes can severely compromise their reliability by underestimating chip-level thermal effects and current flow continuity in pitch matched vias, especially at the local interconnect tier. A more robust via design optimization strategy is proposed which will be useful to process designers.