Design of Asynchronous Digital Systems using Two-Phase Bundled-Data Protocol

Synchronous digital systems have presented serious problems of implementation in DSM (deep sub-micron) VLSI technology, like high noise, high electromagnetic emissions, significant power consuming and a high complexity to define the clock signal distribution. Concerning to these main drawbacks, the asynchronous paradigm shows to be an interesting alternative once, eliminating the clock signal, it is possible to null all the previous cited drawbacks. In this paper it is proposed a practical and simple methodology for the asynchronous digital systems synthesis, starting from the RTL (Register Transfer Level) description of the desired synchronous systems, being these composed by synchronous finite state machine (SFSM) + data-path. The proposed method synthesizes the asynchronous system in the "decomposition style", which is defined by XBM_AFSM (extended burst-mode asynchronous finite state machines) + synchronous data-path. The synthesized asynchronous systems are able to operate in the "two-phase handshake protocol" allowing their better performance. This approach uses the bundled-data style, therefore using CAD tools and components of the synchronous paradigm. Through a case study, it is shown the simplicity of the proposed methodology. The final synthesized circuits show an actual possibility of substituting the synchronous circuits by their asynchronous counterparts, overcoming their major drawbacks.