Challenges of a vintage 1994 CMOS logic chip

The viability of projections for a 1994 CMOS logic chip having 3×10⁵ transistors/cm², 20-W/cm² power dissipation, and 600-MHz clock frequency is assessed with respect to power distribution, signal transmission, and off-chip connections. It is found that current silicon technologies, systematically scaled to 0.25-μm feature size, can achieve complexities of around 2×10 ⁶ transistors/cm², 10-W/cm² power dissipation, and 150-MHz clock frequency. Projected functional throughput rates of 5×10¹³-gate Hz/cm² are inconsistent with these parameters by more than an order of magnitude. Supplying the chips with power at acceptable ΔI noise will pose the most formidable design challenges