DocumentCode :
3130961
Title :
Experimental/numerical analysis of halogen-free printed circuit board assembly under board level drop test
Author :
Zhan, Chau-Jie ; Chang, Hung-Jen ; Chang, Tao-Chih ; Chou, Jung-Hua
Author_Institution :
Electron. & Optoelectron. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
fYear :
2009
fDate :
21-23 Oct. 2009
Firstpage :
381
Lastpage :
384
Abstract :
After the adoption of lead-free electronic products, the halogen-free electronic products are expected to increase in the coming years for environmental protection and green electronics. Currently, for evaluating the drop resistance of handheld electronic products, the board level drop test method is typically employed. In this study, the finite elements analysis was used to analyze the drop responses of totally halogen-free PCBA and the simulation results were verified by drop tests. The outer layers of the halogen-free test board were built-up by resin coated copper (RCC) material. According to the JESD22-B111 standard, five PBGA components with Sn-4Ag-0.5Cu solder balls were mounted on the test board by the Sn-1Ag-0.5Cu solder paste. The ANASYS software was employed to analyze the stress distribution in the joint structures which contained the solder ball, copper pad, and build-up material during drop impacts. The sub-modeling simulation method was used to improve the accuracy and convergence of the simulation results. In addition, by using the support excitation scheme, the contact moment in the impact process during the drop test was translated into effective support excitation loads to simplify the analysis. From the drop test results, failure analysis showed that most of the fractures occurred around the pad on the test board first and then cracks propagated across the outer build-up material. Finally, the inner copper trace was fractured due to the propagated cracks, resulting in the failure of the PCB side. The simulation revealed that the maximum normal stress was located at the outmost solder balls in the PCB side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.
Keywords :
copper alloys; finite element analysis; printed circuit manufacture; printed circuit testing; silver alloys; solders; tin alloys; ANASYS software; JESD22-B111 standard; PBGA components; SnAgCu; board level drop test; build-up material; contact moment; copper pad; crack initiation; drop impacts; drop reliability tests; drop resistance; drop responses; environmental protection; failure analysis; finite elements analysis; green electronics; halogen-free electronic products; halogen-free printed circuit board assembly; halogen-free test board; handheld electronic products; impact process; inner copper trace; lead-free electronic products; numerical analysis; resin coated copper material; solder balls; solder paste; stress distribution; sub-modeling simulation method; support excitation loads; support excitation scheme; totally halogen-free PCBA; Analytical models; Assembly; Circuit testing; Copper; Environmentally friendly manufacturing techniques; Failure analysis; Materials testing; Numerical analysis; Printed circuits; Stress;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microsystems, Packaging, Assembly and Circuits Technology Conference, 2009. IMPACT 2009. 4th International
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-4341-3
Electronic_ISBN :
978-1-4244-4342-0
Type :
conf
DOI :
10.1109/IMPACT.2009.5382197
Filename :
5382197
Link To Document :
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