A meta-interpreter for circuit-extraction

Author

Thirunarayan, Krishnaprasad

Author_Institution

Dept. of Comput. Sci. & Eng., Wright State Univ., Dayton, OH, USA

Volume

2

fYear

1995

fDate

22-26 May 1995

Firstpage

680

Abstract

The design of a VLSI circuit consists of a description of the circuit in terms of its components and subcomponents, at various levels of detail. To verify that the layout of a VLSI circuit conforms to its design, one needs to work backwards from the lowest-level description of the circuit and recognize the higher-level components it constitutes. This paper is concerned with the application of logic programming techniques in the formal verification of the structural correctness of the VLSI circuit layouts. In particular, we review Michael Dukes´ Generalized Extraction System (1990) that compiles design descriptions into a set of extraction rules, and then study the benefits and the limitations of using a meta-interpreter approach to extraction

Keywords

VLSI; integrated circuit layout; logic CAD; logic design; logic programming; Generalized Extraction System; Michael Dukes; VLSI circuit; circuit-extraction; design descriptions; extraction rules; formal verification; logic programming; meta-interpreter; structural correctness; subcomponents; Inverters; Logic circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Aerospace and Electronics Conference, 1995. NAECON 1995., Proceedings of the IEEE 1995 National

Conference_Location

Dayton, OH

ISSN

0547-3578

Print_ISBN

0-7803-2666-0

Type

conf

DOI

10.1109/NAECON.1995.522010

Filename

522010