Stress-induced voiding phenomena for an actual CMOS LSI interconnects

Author

Yoshida, K. ; Fujimaki, T. ; Miyamoto, K. ; Honma, T. ; Kaneko, H. ; Nakazawa, H. ; Morita, M.

Author_Institution

Logic LSI Eng. Dept., Toshiba Microelectron. Corp., Japan

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

753

Lastpage

756

Abstract

Stress induced voiding (SIV) phenomena in Cu damascene interconnect has been studied in detail considering the actual CMOS LSI design for the first time. In order to understand the SIV mechanisms, the test structures were designed to monitor the interconnect pattern dependency, the additional via effectiveness. The SIV in wide metal can be explained by considering effective diffusion area. Also, the SIV occurred in narrow metal line if it has wide metal reservoir, and this is explained. It has been also found that the SIV failure has been drastically reduced by lowering the via anneal temperature.

Keywords

CMOS integrated circuits; annealing; copper; integrated circuit interconnections; integrated circuit testing; large scale integration; voids (solid); CMOS LSI interconnects; Cu; SIV; damascene interconnect; effective diffusion area; interconnect pattern dependency; narrow metal line; stress-induced voiding phenomena; test structures; via anneal temperature; Annealing; CMOS logic circuits; CMOS technology; Chemical vapor deposition; Condition monitoring; Large scale integration; Manufacturing processes; Temperature; Tensile stress; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175947

Filename

1175947