Title :
Test methodology for Freescale´s high performance e600 core based on PowerPC/spl reg/ instruction set architecture
Author :
Tendolkar, Nandu ; Belete, Dawit ; Razdan, Ashu ; Reyes, Hereman ; Schwarz, Bill ; Sullivan, Marie
Author_Institution :
Somerset Design Center, Freescale Semicond.
Abstract :
This paper presents the DFT techniques used in Freescale´s high performance e600 core. Highlights of the DFT features are at-speed logic built-in self-test (LBIST) for delay fault detection, very high test coverage for scan based at-speed deterministic delay-fault test patterns, 100% BIST for embedded memory arrays and 98% stuck-at-fault test coverage for deterministic scan test patterns. A salient design feature is the isolation ring that facilitates testing of the core when it is integrated in an SoC or host processor
Keywords :
automatic test pattern generation; boundary scan testing; built-in self test; discrete Fourier transforms; fault diagnosis; instruction sets; logic testing; microprocessor chips; system-on-chip; DFT techniques; PowerPC; SoC; delay fault detection; delay-fault test patterns; e600 core; embedded memory arrays; host processor; instruction set architecture; logic built-in self-test; scan test patterns; stuck-at fault test coverage; Automatic testing; Built-in self-test; CMOS technology; Clocks; Delay; Design for testability; Fault detection; Logic arrays; Logic design; Logic testing;
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9038-5
DOI :
10.1109/TEST.2005.1583968
