Suppression of stress-induced voiding in copper interconnects

Author

Oshima, T. ; Hinode, K. ; Yamaguchi, H. ; Aoki, H. ; Torii, K. ; Saito, T. ; Ishikawa, K. ; Noguchi, J. ; Fukui, M. ; Nakamura, T. ; Uno, S. ; Tsugane, K. ; Murata, J. ; Kikushima, K. ; Sekisaka, H. ; Murakami, E. ; Okuyama, K. ; Iwasaki, T.

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

757

Lastpage

760

Abstract

Studied stress-induced voiding in Cu interconnects in the temperature range below 250/spl deg/C, and found two different voiding modes. One mode occurs inside a via having wide wire above it, and can be suppressed by optimizing the via shape and the via-cleaning process. The other mode occurs under a via having wide wire below it and can be suppressed by increasing the Cu grain size and improving the adhesion of the barrier metal with Cu.

Keywords

VLSI; adhesion; copper; grain size; integrated circuit interconnections; integrated circuit measurement; integrated circuit reliability; transmission electron microscopy; voids (solid); 150 to 250 degC; Cu; Cu interconnects; adhesion; barrier metal; grain size; multi-level interconnects; stress-induced voiding; via shape; via-cleaning process; voiding modes; Copper; Electric resistance; Integrated circuit interconnections; Laboratories; Mechanical engineering; Shape; Stress; Temperature distribution; Ultra large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175948

Filename

1175948