Identification of systematic yield limiters in complex ASICS through volume structural test fail data visualization and analysis

Traditional yield analysis has been focused on wafer fabrication and process improvement and is generally limited to wafer level visualization. As products get more complex and design practices have more impact on yield, visualization of yield issues inside the chip becomes increasingly critical. This paper presents novel visualization and analysis of volume structural test fail data to aid in the identification of yield weaknesses through relative analysis of fail signatures. The results show that these methodologies can identify subtle process/design yield limiters which cannot be identified using traditional yield analysis methodologies