Title :
Burn-in reduction using principal component analysis
Author :
Nahar, Amit ; Daasch, Robert ; Subramaniam, Suresh
Author_Institution :
Portland State Univ.
Abstract :
A burn-in reduction screen is presented based on a subset of measurements from the wafer sort data. The subset of wafer sort data is identified by a principal component analysis (PCA) using die passing all the tests. This paper addresses the curse of dimensionality and shows the importance of reducing the dimensions in segregating the potential reliability fails for additional screening from the normal healthy population. The method presented is demonstrated using 90nm volume data and compared to 8 hour burn-in experiments
Keywords :
failure analysis; integrated circuit reliability; integrated circuit testing; principal component analysis; 90 nm; burn-in reduction screen; principal component analysis; wafer sort data; CMOS process; CMOS technology; Circuit testing; Costs; Fabrication; Integrated circuit synthesis; Integrated circuit testing; Principal component analysis; Semiconductor device modeling; Stress;
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9038-5
DOI :
10.1109/TEST.2005.1583971
