DocumentCode :
3131155
Title :
Design and simulation study for stacked IC packages with spacer structure
Author :
Wu, Sheng-Tsai ; Hsieh, Ming-Che
Author_Institution :
EOL/Ind. Technol. Res. Inst., Hsinchu, Taiwan
fYear :
2009
fDate :
21-23 Oct. 2009
Firstpage :
419
Lastpage :
422
Abstract :
Most future electronic applications require better reliability and performance as well as lower-priced productions. In order to reach these general demands, three-dimensional (3D) IC packaging technologies are assuming important roles and have been vastly studied in electronic industry. In this investigation, two kinds of designs of experiments (DOE) analysis by wedding finite element analysis (FEA) are carried out to realize effects of material properties of spacers and geometry of stacked IC packages. Through the results, most desirable values of spacers´ material properties and significant geometrical factors in stacked IC packages can be obtained. The simulated results can be most effectively used when optimum stress solutions in stacked IC packages with spacer structure are needed.
Keywords :
design of experiments; finite element analysis; integrated circuit design; integrated circuit packaging; integrated circuit reliability; 3D integrated circuit packaging; designs of experiment analysis; electronic industry; finite element analysis; geometrical factors; integrated circuit reliability; material properties; spacer structure; stacked integrated circuit packages; Electronics industry; Electronics packaging; Finite element methods; Geometry; Integrated circuit packaging; Material properties; Production; Space technology; Stress; US Department of Energy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microsystems, Packaging, Assembly and Circuits Technology Conference, 2009. IMPACT 2009. 4th International
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-4341-3
Electronic_ISBN :
978-1-4244-4342-0
Type :
conf
DOI :
10.1109/IMPACT.2009.5382206
Filename :
5382206
Link To Document :
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