Integration of a 0.13-/spl mu/m CMOS and a high performance self-aligned SiGe HBT featuring low base resistance

Author

Hashimoto, Takashi ; Nonaka, Yusuke ; Saito, Tomohiro ; Sasahara, Kyoko ; Tominari, Tatsuya ; Sakai, Kouki ; Tokunaga, Kazuaki ; Fujiwara, Tsuyoshi ; Wada, Shinichiro ; Udo, Tsutomu ; Jinbo, Tomoko ; Washio, Katsuyoshi ; Hosoe, Hideyuki

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

779

Lastpage

782

Abstract

Without inducing any degradation of CMOS performance and reliability, a high performance self-aligned SiGe-HBT process was successfully integrated to a standard 0.13-/spl mu/m CMOS platform including dual gate oxides and five layers of Al metallization. Suppressing moisture elimination from a wafer surface is a key for reducing thermal budgets during the SiGe HBT formation process. We found that a heavily boron-doped intrinsic base that is highly activated by 1000/spl deg/C RTA improved HBT performance with low r/sub bb/ of 82 /spl Omega/ and high f/sub T//f/sub max/ of 122/178 GHz.

Keywords

BiCMOS integrated circuits; Ge-Si alloys; high-speed integrated circuits; integrated circuit metallisation; integrated circuit reliability; rapid thermal annealing; semiconductor materials; 0.13 micron; 1000 degC; 122 GHz; 178 GHz; 82 ohm; CMOS; RTA; SiGe; SiGe-BiCMOS technologies; base resistance; dual gate oxides; high performance self-aligned HBT; high speed chips; intrinsic base; metallization; moisture elimination; reliability; thermal budgets; wafer surface; Annealing; BiCMOS integrated circuits; Boron; Germanium silicon alloys; Heterojunction bipolar transistors; Impurities; Moisture; Plasma temperature; Resistors; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175954

Filename

1175954