Structural tests for jitter tolerance in SerDes receivers

A suite of structural tests is described that uses on-chip under sampling to measure parameters that affect jitter tolerance in a multi-gigabit-per-second (Gbps) receiver. The tests measure high-frequency jitter (RMS value and histogram) in the received signal and in the recovered clock, plus transition-density dependent phase-shift, mean sampling position in the signal eye, sampling clock phase error, and pin-to-pin skew, all with near-picosecond resolution and repeatability, in tens of milliseconds. Hardware results for a 3 Gbps serializer/ deserializer (SerDes) IC are included. The new method is suitable for an unlimited number of channels, it simplifies test hardware, it reduces production test time, and is suitable for any tester. The diagnostic capabilities facilitate improving yield and quality