Test time reduction of successive approximation register A/D converter by selective code measurement

This paper proposes a novel methodology for reducing the static linearity test time of SAR A/D converters. Due to the low data conversion rate and high resolution, the test time required measuring the linearity specifications such as INL and DNL in SAR A/D converters can be as high as 40% of the total A/D converter test time. The proposed method is based on the fact that the non-idealities in the code widths of the converter are correlated to and are dominated by the manufacturing variations in specific components used in the A/D converter design. Therefore, by measuring a subset of the total set of code widths that are directly affected by manufacturing variations in these components, all the code widths are estimated accurately. As opposed to prior work, the proposed approach does not use linear error models and describes a method which directly measures the code widths using a piecewise linear ramp designed to extract test information accurately from the relevant codes. The proposed method has been applied to a SAR A/D converter in production with achieved test time reduction of more than 75%