Reducing routing congestion in a cryptographic IP core using NoC interconnect

On-chip data traffic in coding and cryptographic circuits often consists of very long words or large groups of smaller words exchanged between processing elements. The resulting wide cross-chip buses exhibit congestion, power and scalability problems. In this paper, we report on a case study IP core for Identity-based Encryption which has been implemented in 65nm CMOS. Problematic wide buses are replaced by a simple circuit-switched NoC-style interconnect. Congestion is reduced dramatically, allowing higher utilisation and resulting in lower switching power and better reliability. The results have applicability to wire-constrained designs in other domains.