Author :
Park, Y.K. ; Cho, C.H. ; Lee, K.H. ; Roh, B.H. ; Ahn, Y.S. ; Lee, S.H. ; Oh, J.H. ; Lee, J.G. ; Kwak, D.H. ; Shin, S.H. ; Bae, J.S. ; Kim, S.B. ; Lee, J.K. ; Lee, J.Y. ; Kim, M.S. ; Lee, J.W. ; Lee, D.J. ; Hong, S.H. ; Bae, D.I. ; Chun, Y.S. ; Park, S.H.
Author_Institution :
Semicond. R&D Div., Samsung Electron. Co. Ltd., Kyunggi-Do, South Korea
Abstract :
A 90 nm DRAM technology has been successfully developed using 512 Mb DRAM for the first time. ArF lithography is used for printing critical layers with resolution enhancement techniques. A novel gap-filling technology using spin coating oxide is developed for STI and ILD processes. A diamond-shaped storage node is newly developed for large capacitor area with better mechanical stability. A CVD Al process can make the back-end metallization process simple and easy. A dual gate oxide scheme can provide independent optimization for memory cell transistor and periphery support device so that the off-state leakage current of the cell transistor can be maintained below 0.1 fA.
Keywords :
DRAM chips; VLSI; integrated circuit manufacture; integrated circuit technology; leakage currents; nanotechnology; ultraviolet lithography; 0.1 fA; 512 Mbit; 90 nm; Al; ArF; ArF lithography; CVD Al process; DRAM technology; ILD process; STI process; back-end metallization process; cell transistor off-state leakage current; diamond-shaped storage node; dual gate oxide scheme; dynamic RAM; gap-filling technology; large capacitor area; mechanical stability; memory cell transistor optimization; periphery support device optimization; resolution enhancement techniques; spin coating oxide; Artificial intelligence; Capacitors; Dry etching; Lithography; Manufacturing; Material storage; Printing; Random access memory; Research and development; Transistors;
