Calibrating clock stretch during AC scan testing

Author

Rearick, Jeff ; Rodgers, Richard

Author_Institution

Agilent Technol., Fort Collins, CO

fYear

2005

fDate

8-8 Nov. 2005

Lastpage

273

Abstract

Delay fault testing via AC scan is shown to suffer from test application problems that, if not accounted for, will cause a reduction in test quality. The problem of clock period stretching is demonstrated, and a novel circuit for calibrating this effect is described. Guidelines for AC scan test application on the tester to improve the quality of AC scan tests are presented, along with results from several large ASICs

Keywords

boundary scan testing; clocks; fault simulation; AC scan testing; clock period stretching; clock stretch calibration; delay fault testing; Circuit faults; Circuit testing; Clocks; Delay effects; Electrical fault detection; Fault detection; Guidelines; Logic testing; Propagation delay; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2005. Proceedings. ITC 2005. IEEE International

Conference_Location

Austin, TX

Print_ISBN

0-7803-9038-5

Type

conf

DOI

10.1109/TEST.2005.1583984

Filename

1583984

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3131363