Interlayer dielectric (ILD)-related edge channel effect in high density DRAM cell

A DRAM cell for suppressing anomalous threshold voltage (VT) lowering due to ILD-related edge channel effect is intensively investigated. Our work verifies that the anomalous edge channel effect in a 0.15 /spl mu/m-DRAM cell is mainly attributed to positive charge in the Si/SiO/sub 2/ interface originating from ILD-contained hydrogen and moisture. In addition, on the basis of the hydronium-like model, five process schemes to overcome the anomalous edge channel effect, are independently suggested: (1) outgassing prior to stopper Si/sub 3/N/sub 4/, (2) cutting off migration path (3) using high temperature oxide (HTO) as gate inner sidewall (SW) spacer, (4) Si-rich high density plasma (HDP) process and (5) incorporating the appropriate quantity of fluorine during the ILD HDP process.