Title :
Ultra-high-performance 0.13-/spl mu/m embedded DRAM technology using TiN/HfO2/TiN/W capacitor and body-slightly-tied SOI
Author :
Aoki, Y. ; Ueda, T. ; Shirai, H. ; Sakoh, T. ; Kitamura, T. ; Arai, S. ; Sakao, M. ; Inoue, K. ; Takeuchi, M. ; Sugimura, H. ; Hamada, M. ; Wake, T. ; Naritake, I. ; Iizuka, T. ; Yamamoto, T. ; Ando, K. ; Noda, K.
Author_Institution :
ULSI Device Dev. Div., NEC Corp., Kanagawa, Japan
Abstract :
We present an ultra-high-performance 0.13-/spl mu/m embedded DRAM technology, which improves transistor performance in both logic devices and DRAM cells. Simulation results indicate that the typical random access cycle of a 16-Mbit DRAM core exceeds 570 MHz. The full-metal DRAM structure having a newly developed TiN/HfO/sub 2//TiN/W capacitor minimizes the aspect ratio of the cylindrical capacitor electrode to reduce contact resistance in the logic area. Integration of the embedded DRAM with BSTSOI (Body-Slightly-Tied SOI) is also demonstrated, with which the logic performance can be further improved and the DRAM cell area is free from floating-body effects.
Keywords :
CMOS memory circuits; MIM devices; VLSI; capacitors; integrated circuit technology; random-access storage; silicon-on-insulator; 0.13 micron; 16 Mbit; 570 MHz; DRAM cells; DRAM core; Si; TiN-HfO/sub 2/-TiN-W; TiN/HfO/sub 2//TiN/W MIM capacitor; body-slightly-tied SOI; contact resistance reduction; cylindrical capacitor electrode; embedded DRAM technology; full-metal DRAM structure; logic devices; random access cycle; transistor performance improvement; ultra-high-performance DRAM technology; CMOS process; Contact resistance; Electrodes; Fabrication; Hafnium oxide; Leakage current; Logic devices; MIM capacitors; Random access memory; Tin;
Conference_Titel :
Electron Devices Meeting, 2002. IEDM '02. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7462-2
DOI :
10.1109/IEDM.2002.1175966
