High performance cell technology featuring sub-100nm DRAM with multi-gigabit density

Author

Byung-Chan Lee ; Jong-Ryeol Yoo ; Deok-Hyung Lee ; Cheol-Sung Kim ; In-Soo Jung ; Siyoung Choi ; U-In Chung ; Joo-Tae Moon

Author_Institution

Semicond. R&D Center, Samsung Electron. Co. Ltd., Kyungki-Do, South Korea

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

835

Lastpage

838

Abstract

Fully metal embedded cell technologies, including poly-Si/W/sub x/N/W gate, Co salicide with elevated source/drain using UHV-selective epitaxial growth and CVD-W cell pad has been integrated successfully for the first time for 100 nm design rule DRAM devices. Each key technology exhibits excellent performance.

Keywords

CMOS memory circuits; DRAM chips; MOSFET; chemical mechanical polishing; chemical vapour deposition; contact resistance; integrated circuit metallisation; leakage currents; vapour phase epitaxial growth; 100 nm; 100 nm design rule DRAM devices; CMP; CVD-W cell pad; Co salicide; CoSi/sub 2/; MOSFET performance; Si-W/sub x/N-W; UHV-selective epitaxial growth; elevated source/drain; fully metal embedded cell technologies; high performance cell technology; multi-gigabit density; poly-Si/W/sub x/N/W gate; sub-100nm DRAM; Circuits; Contact resistance; Electrical resistance measurement; Epitaxial growth; Graphics; Low voltage; Moon; Parasitic capacitance; Random access memory; Research and development;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175967

Filename

1175967