Title :
A fully integrated Al2O3 trench capacitor DRAM for sub-100 nm technology
Author :
Seidl, H. ; Gutsche, M. ; Schroeder, U. ; Birner, A. ; Hecht, T. ; Jakschik, S. ; Luetzen, J. ; Kerber, M. ; Kudelka, S. ; Popp, T. ; Orth, A. ; Reisinger, H. ; Saenger, A. ; Schupke, K. ; Sell, B.
Author_Institution :
Infineon Technol., Munich, Germany
Abstract :
For the first time, fully integrated 128 Mb trench DRAMs using Al/sub 2/O/sub 3/ as high-k node dielectric in silicon-insulator-silicon (SIS) capacitors were successfully fabricated. A highly manufacturable integration scheme for Al/sub 2/O/sub 3/ as node dielectric in trench capacitors was developed and successfully implemented in a 170 nm ground rule technology. A capacitance close to 50 fF/cell with leakage current well below 1 fA/cell was achieved, leading to significantly improved retention characteristics. 128 Mb DRAM devices with full functionality and excellent test yields were obtained. The scalability of this technology to smaller dimensions is demonstrated by the integration of ALD (Atomic Layer Deposition) Al/sub 2/O/sub 3/ into 110 nm ground rule trench capacitors. In addition, trench capacitors with Al/sub 2/O/sub 3/ on hemispherical grain (HSG) silicon were fabricated, exhibiting high capacitance enhancement with low leakage current.
Keywords :
CMOS memory circuits; DRAM chips; alumina; capacitance; capacitors; dielectric thin films; integrated circuit yield; leakage currents; semiconductor-insulator-semiconductor devices; 1 fA; 100 nm; 110 nm; 110 nm ground rule trench capacitors; 128 Mbit; 170 nm; 170 nm ground rule technology; 50 fF; Al/sub 2/O/sub 3/ high-k node dielectric; Al/sub 2/O/sub 3/-Si; atomic layer deposition Al/sub 2/O/sub 3/; capacitance enhancement; fully integrated 128 Mb trench DRAMs; fully integrated Al/sub 2/O/sub 3/ trench capacitor DRAM; hemispherical grain silicon; leakage current; manufacturable integration scheme; retention characteristics; silicon-insulator-silicon capacitors; sub-100 nm technology; technology scalability; test yields; Atomic layer deposition; Capacitance; Capacitors; High K dielectric materials; High-K gate dielectrics; Leakage current; Manufacturing; Random access memory; Scalability; Testing;
Conference_Titel :
Electron Devices Meeting, 2002. IEDM '02. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7462-2
DOI :
10.1109/IEDM.2002.1175968
