Title :
A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer
Author :
Arasu, S.T. ; Ravikumar, C.P. ; Nandy, S.K.
Author_Institution :
ASIC Dept., Texas Instrum. India, Bangalore
Abstract :
We propose a clock-domain-based partitioning technique for practicing scan test in large system-on-chips with multiple clock domains with the intent of reducing test application time and test power
Keywords :
boundary scan testing; divide and conquer methods; logic partitioning; low-power electronics; system-on-chip; multiclock domain; partitioning technique; scan test architecture; system-on-chip; test application time; virtual divide and conquer; Automatic testing; Built-in self-test; Circuit testing; Clocks; Computer architecture; Costs; Design for testability; Logic testing; System testing; System-on-a-chip;
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9038-5
DOI :
10.1109/TEST.2005.1583995
