DocumentCode
3131601
Title
A novel process and hardware architecture to reduce burn-in cost
Author
Schroeder, Chris ; Pan, Jin ; Albertson, Todd
fYear
2005
fDate
8-8 Nov. 2005
Lastpage
437
Abstract
This paper presents a novel process and hardware architecture that dramatically reduces the cost of burn-in for performance CPUs. This also demonstrates that Moore´s law can be sustained for BI in face of many challenges
Keywords
integrated circuit testing; microprocessor chips; Moore law; burn-in cost reduction; hardware architecture; process architecture; Acceleration; Bismuth; Cogeneration; Costs; Hardware; Manufacturing; Temperature distribution; Testing; Thermal stresses; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location
Austin, TX
Print_ISBN
0-7803-9038-5
Type
conf
DOI
10.1109/TEST.2005.1584002
Filename
1584002
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