Power-supply noise in SoCs: ATPG, estimation and control

Noise on the power-supply lines has become a critical factor especially in low-voltage designs as excessive noise may cause intermittent functional error and eventually system failure. Having a realistic picture of the worst case noise throughout a chip is important as we can devise a remedy to alleviate the problem before it becomes too late. This paper provides a fast automatic pattern generation method to estimate the maximum simultaneous switching noise for a non-embedded core. When the cores are integrated within a SoC, the combined noise is far from a simple additive behavior. We offer a heuristic to estimate the power-supply noise in core-based SoCs. This heuristic can be employed to minimize the number of power-supply lines/pins while keeping the noise under control. The experiments using ISCAS´85 benchmarks verify that our power-supply noise methodology is fairly fast and accurate and can be used for effective power-supply distribution