Title :
IEEE 1500 utilization in SOC design and test
Author :
Zorian, Yervant ; Yessayan, Avetik
Author_Institution :
Virage Logic, Corp., Fremont, CA
Abstract :
Integrating numerous IP cores into a SoC design is a complex activity from the design-for-testability point of view. Also, accessing and exercising test and diagnosis patterns on each IP core during the manufacturing phases is a major challenge. Designing the IEEE 1500 standard into the IP core and leveraging it during the DFT integration and manufacturing phases drastically simplify these challenges. This paper demonstrates the use of IEEE 1500 in embedded memory IP cores, and describes how it can be leveraged in a SoC during its design and manufacturing phases
Keywords :
IEEE standards; design for testability; integrated circuit design; integrated circuit testing; system-on-chip; IEEE 1500 standard; Internet protocol cores; SoC; design-for-testability; system-on-chip; Built-in self-test; Cost function; Design for testability; Design methodology; Integrated circuit testing; Logic design; Logic testing; Pulp manufacturing; Redundancy; USA Councils;
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9038-5
DOI :
10.1109/TEST.2005.1584015
