F-Timer: dedicated FPGA to real-time systems design support

Author

Parisoto, A. ; Souza, A., Jr. ; Carro, L. ; Pontremoli, M. ; Pereira, C. ; Suzim, A.

Author_Institution

Electr. Eng. Dept., Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil

fYear

1997

fDate

11-13 Jun 1997

Firstpage

35

Lastpage

40

Abstract

This paper presents a hardware architecture and its FPGA implementation for real-time operating systems support. Dedicated hardware units are responsible for the maintenance of a 32 tasks list organized by time priority. The co-processor also communicates with the microprocessor to program interrupt modes and tasks. This dedicated HW architecture was easily prototyped in modern FPGAs, being a cost-effective solution to free microcontrollers from the burden of task time management. The FPGA has been completely synthesized based on a HDL description, allowing its use as a macrocell in larger designs. The task resolution is of 100 μs

Keywords

computer architecture; coprocessors; field programmable gate arrays; hardware description languages; high level synthesis; interrupts; microprocessor chips; operating systems (computers); real-time systems; F-Timer; HDL description; coprocessor; cost-effective; dedicated FPGA; dedicated hardware units; hardware architecture; hardware prototyping; interrupt modes; logic design; macrocell; maintenance; microcontrollers; microprocessor; real-time operating systems; real-time systems design support; task time management; time priority; Automatic control; Clocks; Control systems; Field programmable gate arrays; Hardware; Job shop scheduling; Operating systems; Process control; Processor scheduling; Real time systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Real-Time Systems, 1997. Proceedings., Ninth Euromicro Workshop on

Conference_Location

Toledo

Print_ISBN

0-8186-8034-2

Type

conf

DOI

10.1109/EMWRTS.1997.613761

Filename

613761