An improved implementation of Montgomery algorithm using efficient pipelining and structured parallelism techniques

The Montgomery modular multiplication plays an important role in public-key encryption algorithm. We present an efficient hardware implementation of Montgomery algorithm. Regarding its application in RSA, we also present two techniques for more efficient implementation of modular exponentiation. The experiment results show that by reducing the number of operations in implementing Montgomery modular multiplication and modular exponentiation, it could work faster and be more power ef. The algorithms are implemented in Verilog HDL and simulated in Modelsim to verify the results. The synthesis process is performed based on Altera Stratix III FPGA in Quartus II. With the help of Stratix PowerPlay Early Power Estimator, we are able to evaluate the power consumption.