Test data compression for IP embedded cores using selective encoding of scan slices

We present a selective encoding method that reduces test data volume and test application time for scan testing of intellectual property (IP) cores. This method encodes the slices of test data that are fed to the scan chains in every clock cycle. Unlike many prior methods, the proposed method does not encode all the specified (0s and 1s) and unspecified (don´t-care) bits in a slice. For example, if a slice contains more 1s than 0s, only the 0s are encoded and all don´t-cares are mapped to 1. We use only c tester channels, where c = [log₂(N + 1)] + 2, to drive N scan chains. In the best case, we can achieve compression by a factor of N/c using only one tester clock cycle per slice. We derive an upper bound on the density of care bits (either 1s or 0s) that allows us to achieve the best-case compression. The pattern decompression is of the continuous-flow type because no complex handshakes are required between the tester and the chip. Unlike popular compression methods such as EDT and SmartBIST, the proposed approach is suitable for IP cores because it does not require structural information for fault simulation, dynamic compaction, or interleaved test generation. The on-chip decoder is small, independent of the circuit under test and the test set, and it can be shared between different circuits. We present compression results for a number of industrial circuits, and compare our results to other recent compression methods targeted at IP cores. We show that up to 28times reduction in test data volume and 20times reduction in testing time is obtained for these circuits