Title :
Definition of a robust modular SOC test architecture; resurrection of the single TAM daisy-chain
Author :
Waayers, Tom ; Morren, Richard ; Grandi, Roberto
Author_Institution :
Philips Res. Labs., High Tech Campus, Eindhoven
Abstract :
This paper presents a new modular SOC test architecture that uses an improved single TAM daisy-chain for scan test access to embedded modules. The architecture by definition guarantees that the total SOC test time is close to the lower bound. To make third party IP cores to fit the architecture, IP with test infrastructure ´on-demand´ is introduced. An area-efficient bypass implementation for our IEEE std. 1500 compliant test wrapper is presented and results from a single TAM daisy-chain on silicon are shown
Keywords :
IEEE standards; boundary scan testing; embedded systems; integrated circuit design; integrated circuit testing; logic testing; silicon; system-on-chip; IEEE 1500 standards; Si; compliant test wrapper; embedded modules; intellectual property cores; scan test access; system-on-chip test architecture; test access mechanism daisy-chain; Buildings; Laboratories; Logic testing; Manufacturing; Merging; Robustness; Semiconductor device testing; Silicon; System testing; System-on-a-chip;
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9038-5
DOI :
10.1109/TEST.2005.1584022
