Impact of new materials, changes in physics and continued ULSI scaling on failure mechanisms and analysis

Author

Nishi, Yoshio ; McPherson, J.W.

Author_Institution

Silicon Technol. R&D, Texas Instrum. Inc., Dallas, TX, USA

fYear

1999

fDate

1999

Firstpage

1

Lastpage

8

Abstract

Scaling has pushed existing CMOS materials to their physical and reliability limits. New materials such as Cu, low-k interconnect dielectrics, and high-k gate dielectrics are required if the historical scaling rate is to continue. The benefits and trade-offs associated with these new CMOS materials introductions are discussed

Keywords

CMOS integrated circuits; ULSI; dielectric thin films; failure analysis; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; permittivity; technological forecasting; CMOS material physics; CMOS materials; CMOS materials introduction; Cu; Cu metallisation; ULSI scaling; failure analysis; failure mechanisms; high-k gate dielectrics; low-k interconnect dielectrics; physical limits; reliability limits; scaling rate; CMOS technology; Dielectric materials; Failure analysis; High K dielectric materials; Integrated circuit interconnections; Marketing and sales; Materials reliability; Physics; Silicon; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 1999. Proceedings of the 1999 7th International Symposium on the

Print_ISBN

0-7803-5187-8

Type

conf

DOI

10.1109/IPFA.1999.791192

Filename

791192