Title :
Built-in constraint resolution
Author :
Giles, Grady ; Irby, Joel ; Toneva, Daniela ; Tsai, Kun-Han
Abstract :
A scan circuit construction obviates ATPG constraints for the prevention of tristate contention on internal tristate busses and one-hot muxes. The circuit is supported by enhanced ATPG
Keywords :
automatic test pattern generation; built-in self test; logic testing; ATPG constraints; built-in constraint resolution; one-hot muxes; scan circuit; tristate busses; tristate contention; Automatic test pattern generation; Circuit testing; Clocks; Decoding; Driver circuits; Microprocessors; Sequential analysis; System testing; Timing; Very large scale integration;
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9038-5
DOI :
10.1109/TEST.2005.1584032
