• DocumentCode
    3132226
  • Title

    Random defect limited yield using a deterministic model

  • Author

    Singh, Anthony ; Rosin, Jon

  • Author_Institution
    Dominion Semicond. LLC, Manassas, VA, USA
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    161
  • Lastpage
    165
  • Abstract
    To be successful in the competitive semiconductor industry, the need to reduce cost per die is necessary and always challenging. It is important to produce better die per wafer by minimizing the cycle time to detect and fix yield problems associated with the technology. Yield, or wafer sort yield (number of good chips/wafer) can be separated into three components: random defect limited yield, systematic yield, and repeating yield loss. Random defect limited yield is caused by defects. Process equipment and byproducts primarily cause defects. Defects, usually randomly distributed, can also be localized to one, or multiple die on a wafer. In-line QC inspection tools can detect most defects. Systematic yield losses are process-related problems that can affect all die on a wafer, some die on a wafer, or die by region on a wafer. Systematic yield losses are not detectable by in-line QC defect inspection tools. Repeating yield loss is due to reticle defects. Reticle defects occur on the same die within a reticle field, e.g. a repeating defect can be caused by contamination on the stepper lens, by contamination on the pellicle that protects the reticle, or by contamination on the reticle itself. Reticle defects are sometimes detectable by in-line QC inspection tools. The focus of this paper is on the calculations and results of random defect limited yield (DLY) using the deterministic yield model. This model is used to prioritize defect problems, and to drive yield improvements. Examples are used to illustrate the benefits and strengths of the deterministic model. We also discuss the methodology, assumptions, and limitations of this model
  • Keywords
    fault location; inspection; integrated circuit reliability; integrated circuit testing; integrated circuit yield; photolithography; quality control; reticles; semiconductor process modelling; surface contamination; cost per die; cycle time minimization; defect localization; defect problem prioritization; deterministic model; deterministic yield model; in-line QC defect inspection tools; in-line QC inspection tools; pellicle contamination; process equipment; process equipment byproducts; process-related problems; random defect limited yield; randomly distributed defects; repeating defect; repeating yield loss; reticle contamination; reticle defects; reticle field; semiconductor industry; stepper lens contamination; systematic yield; systematic yield losses; wafer sort yield; yield improvement; yield problem detection; Automatic optical inspection; Circuits; Contamination; Electronics industry; Optical microscopy; Optical sensors; Predictive models; Scanning electron microscopy; Semiconductor device modeling; Semiconductor process modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Semiconductor Manufacturing Conference, 2001 IEEE/SEMI
  • Conference_Location
    Munich
  • ISSN
    1078-8743
  • Print_ISBN
    0-7803-6555-0
  • Type

    conf

  • DOI
    10.1109/ASMC.2001.925641
  • Filename
    925641