Compressed pattern diagnosis for scan chain failures

In scan based designs, 10%-30% defects are in scan chains. Hence scan chain fault diagnosis becomes an important process for silicon debug and yield ramp up. With embedded compression techniques getting popular, chain diagnosis on devices with the embedded compression techniques becomes a challenge. In this paper, we provide a general methodology that can be applied for performing chain diagnosis in the context of any embedded compression techniques with any existing chain diagnosis algorithms. The proposed methodology enables seamless reuse of the existing chain diagnosis infrastructure with compressed test data. Experimental results show that with compressed patterns, the chain diagnosis resolution can be enhanced up to one order of magnitude with only 25% of failure cycles collected from ATE, compared to the diagnosis results with uncompressed patterns