IJTAG (internal JTAG): a step toward a DFT standard

Author

Rearick, Jeff ; Eklow, Bill ; Posse, Ken ; Crouch, Al ; Bennetts, Ben

Author_Institution

Agilent Technol., Fort Collins, CO

fYear

2005

fDate

8-8 Nov. 2005

Lastpage

815

Abstract

The widespread use of the IEEE 1149.1 standard test access port as the interface for not only boundary scan but also for access to device-internal test features has led to a highly useful but highly fragmented opportunity for the test community. The need for a standard description of internal test features and protocols is elucidated, and the framework for the extension of the boundary scan standards as launched by the ad hoc IJTAG working group is described

Keywords

IEEE standards; boundary scan testing; design for testability; DFT standard; IEEE 1149.1; ad hoc IJTAG; boundary scan standards; boundary scan test; design for testability; device-internal test features; internal JTAG; internal test protocols; standard description; standard test access port; Access protocols; Built-in self-test; Circuit testing; Clocks; Integrated circuit interconnections; Logic testing; Memory management; Pins; Printed circuits; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2005. Proceedings. ITC 2005. IEEE International

Conference_Location

Austin, TX

Print_ISBN

0-7803-9038-5

Type

conf

DOI

10.1109/TEST.2005.1584044

Filename

1584044

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3132369