Fixed priority timing analysis of real-time systems with limited parallelism

Conventional real-time system implementations assume a von Neumann processor-memory architecture with at most one software process executing at any time. Scheduling approaches for such systems multiplex the processor among runnable processes. Fixed priority scheduling, notably, utilises timing analysis to determine offline the run-time timing behaviour of the system. Recent alternative real-time system implementations combine processor-memory architectures with reconfigurable hardware for speedup. Such reconfigurable hardware can execute many functions in parallel. This leads to a limited parallel system where a single software process can execute on the processor at any time, in parallel with a number of functions implemented in hardware. Conventional fixed priority timing analysis is unsuitable for this model, as fundamental assumptions are compromised, e.g. the notion of a critical instant. This paper proposes new timing analysis aimed at such limited parallel systems, illustrated by an example system utilising field programmable gate arrays as the reconfigurable hardware resource.