Title :
Testing priority address encoder faults of content addressable memories
Author_Institution :
Dept. of Electr. Eng., National Central Univ., Jungli
Abstract :
Content addressable memory (CAM) is one key component in many digital systems. Although the CAM cell usually is implemented with RAM cell and comparison logic, the CAM testing is more difficult than the RAM testing. Also, the CAM testing is very different from the RAM testing. Most stuck-at faults (SAFs) in the RAM peripheral circuitry can be mapped to the RAM cell faults. This cannot be analogous to the testing of the priority encoder of CAMs. This paper presents a test algorithm for testing SAFs of the priority encoder in a CAM. The test algorithm only requires 3N - 2 Write operations and N + 2 compare operations to cover 100% stuck-at faults of the CMOS priority encoder of an N times B-bit CAM. Compared with typical tests for CAM cell array faults, the fault coverage of SAFs in the priority encoder is increased from 90.2% or 60.5% to 100% for a CAM with 64 words
Keywords :
built-in self test; circuit testing; content-addressable storage; fault diagnosis; logic testing; BIST; CAM cell array faults; CAM testing; CMOS priority encoder; RAM cell faults; RAM peripheral circuitry; RAM testing; SAF testing; built in self test; comparison faults; comparison logic; content addressable memories; fault coverage; priority address encoder faults; stuck-at fault testing; Associative memory; Built-in self-test; CADCAM; Circuit faults; Circuit testing; Computer aided manufacturing; Electrical fault detection; Fault detection; Random access memory; Read-write memory;
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9038-5
DOI :
10.1109/TEST.2005.1584046
