Chasing subtle embedded RAM defects for nanometer technologies

Author

Powell, Theo ; Kumar, Amrendra ; Rayhawk, Joseph ; Mukherjee, Nilanjan

Author_Institution

Texas Instrum. Inc., Dallas, TX

fYear

2005

fDate

8-8 Nov. 2005

Lastpage

850

Abstract

A design´s increasing density, as well as its number of embedded memories increases its vulnerability to a variety of potential manufacturing defects. Standard March test algorithms used for obtaining good defect coverage must be augmented by new algorithms that target defects not screened by embedded BIST controllers. This paper presents our experience diagnosing address decode open faults (ADOF) using scan patterns. Subsequently, tests were added in the BIST controller to target ADOF. Other tests were added to screen potential bit/byte write-enable faults in memories with bit/byte write-enable controls

Keywords

built-in self test; fault diagnosis; logic testing; nanotechnology; random-access storage; ADOF; BIST controller; address decode open faults; defect coverage; embedded RAM defects; manufacturing defects; nanometer technologies; scan patterns; standard March test; write-enable controls; write-enable faults; Built-in self-test; Circuit faults; Circuit testing; Decoding; Fault detection; Graphics; Instruments; MOSFETs; Manufacturing; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2005. Proceedings. ITC 2005. IEEE International

Conference_Location

Austin, TX

Print_ISBN

0-7803-9038-5

Type

conf

DOI

10.1109/TEST.2005.1584048

Filename

1584048