Title :
Lowering the cost of test with a scalable ATE custom processor and timing IC containing 400 high-linearity timing verniers
Author_Institution :
Credence Syst. Corp., Milpitas, CA
Abstract :
This paper presents the architecture of the Omni ASIC, a highly integrated and scalable ATE processor and timing IC. This ASIC includes a complete pattern generator and 50 channels of timing, format, and fail processing. The IC includes 400 low-power timing verniers with a linearity error of less then 30 ps
Keywords :
application specific integrated circuits; automatic test equipment; automatic test pattern generation; low-power electronics; microprocessor chips; timing circuits; Omni ASIC; automatic test equipment; high-linearity timing verniers; low-power timing verniers; pattern generator; scalable ATE processor; timing IC; timing integrated circuit; Application specific integrated circuits; Circuit testing; Cost function; Electronic equipment testing; Integrated circuit testing; Linearity; Power generation; System testing; Test pattern generators; Timing;
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9038-5
DOI :
10.1109/TEST.2005.1584052
