Title :
Simulation of transients caused by single-event upsets in combinational logic
Author :
Mohanram, Kartik
Author_Institution :
Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX
Abstract :
A comprehensive technique for simulation of transients caused by single-event upsets (SEUs) in combinational logic circuits is described. Based upon linear RC models of gates, the proposed technique integrates a closed-form model for computation of the SEU-induced transient at the site of a particle strike with propagation models for the transients along a functionally sensitized path. A full set of simulation results indicate that on average, the models are accurate to within 10% of the results obtained using SPICE simulations (peak magnitude and duration about 0.5VDD) with over 1000times improvement in computational speed
Keywords :
RC circuits; combinational circuits; fault simulation; logic testing; radiation effects; transient analysis; SEU; combinational logic circuits; linear RC models; logic gates; particle strike; single-event upset; transient simulation; Circuit simulation; Combinational circuits; Computational modeling; Computer simulation; Error analysis; Integrated circuit reliability; Logic; SPICE; Single event transient; Single event upset;
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9038-5
DOI :
10.1109/TEST.2005.1584063
