Generalizing timing predictions to set-associative caches

Research on the static prediction of worst-case execution time (WCET) of programs has been extended from simple CISC to pipelined RISC processors, and from uncached architectures to direct-mapped instruction caches. This work goes one step further by introducing a framework to handle WCET prediction for set-associative caches. Generalizing the work of static cache simulation of direct-mapped caches to set-associative caches, a formalization of the new method is given and the operational characteristics are presented and discussed by example. WCET predictions for several programs are presented by combining the static cache analysis for set-associative caches with a timing analysis tool. This approach has the advantage that cache configuration details are handled by static cache simulation but remain transparent to the timing analyzer. It is shown that static cache analysis for set-associative caches results in just as tight timing predictions as reported for direct-mapped caches. Overall, this work fills another gap between realistic WCET prediction of contemporary architectures and its use in schedulability analysis for hard real-time systems