Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems

Author

Robertson, Iain ; Hetherington, Graham ; Leslie, Tom ; Parulkar, Ishwar ; Lesnikoski, Ronald

Author_Institution

Texas Instruments, Inc., Dallas, TX

fYear

2005

fDate

8-8 Nov. 2005

Lastpage

999

Abstract

Throughput computing requires chip I/O bandwidth of the order of Tbits/sec which can be met by high speed, large scale implementation of SerDes I/Os (serial/deserial differential I/Os with clock embedded in data stream). The traditional test philosophy and existing ATE do not meet the challenges of testing chip interfaces with few hundreds of I/Os operating at multi-Gbps. In this paper, we present the test challenges and describe on-chip DFT modes and new ATE directions for chip level characterization and test of such interfaces used in throughput computing chip sets

Keywords

computer testing; design for testability; high-speed integrated circuits; integrated circuit layout; integrated circuit testing; microprocessor chips; system buses; ATE; SerDes I-O; automatic test equipment; clock embedded data stream; design for testability; high-speed implementation; integrated circuit testing; large scale implementation; on-chip DFT modes; serial-deserial differential I-O; testing chip interfaces; throughput computing systems; Bandwidth; Computer architecture; Hip; Large-scale systems; Protocols; Silicon; Sun; System testing; Throughput; Yarn;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2005. Proceedings. ITC 2005. IEEE International

Conference_Location

Austin, TX

Print_ISBN

0-7803-9038-5

Type

conf

DOI

10.1109/TEST.2005.1584065

Filename

1584065