167 MHz radix-4 floating point multiplier

Author

Yu, Robert K. ; Zyner, Gregory B.

Author_Institution

SPARC Technol. Bus., Sun Microsyst. Inc., Sunnyvale, CA, USA

fYear

1995

fDate

19-21 Jul 1995

Firstpage

149

Lastpage

154

Abstract

An IEEE floating point multiplier with partial support for subnormal operands and results is presented. Radix-4 or modified Booth encoding and a binary tree of 4:2 compressors are used to generate the 53×53 double-precision product. Delay matching techniques were used in the binary tree stage and in the final addition stage to reduce cycle time. New techniques in rounding and sticky-bit generation were also used to reduce area and timing. The overall multiplier has a latency of 3 cycles a throughput of 1 cycle, and a cycle time of 6.0 ns. This multiplier has been implemented in a 0.5 μm static CMOS technology in the UltraSPARC RISC microprocessor

Keywords

CMOS integrated circuits; encoding; floating point arithmetic; multiplying circuits; reduced instruction set computing; 0.5 μm static CMOS technology; 0.5 micron; 167 MHz; 6 ns; IEEE; UltraSPARC RISC microprocessor; binary tree; delay matching techniques; double-precision product; modified Booth encoding; radix-4 floating point multiplier; sticky-bit generation; subnormal operands; Binary trees; CMOS technology; Delay effects; Encoding; Modems; Reduced instruction set computing; Signal processing; Sun; Throughput; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Arithmetic, 1995., Proceedings of the 12th Symposium on

Conference_Location

Bath

Print_ISBN

0-8186-7089-4

Type

conf

DOI

10.1109/ARITH.1995.465364

Filename

465364