Title :
Predicting pipelining and caching behaviour of hard real-time programs
Author :
Stappert, Friedhelm
Author_Institution :
C-LAB, Paderborn, Germany
Abstract :
A new system for the instruction level timing analysis of hard real time programs is presented. The analysis exploits the very simple structure of these programs, resulting in a considerable processing time improvement compared to general case analysis techniques. The new analysis system covers all speed up mechanisms used for modern superscalar processors at once: pipelining, data caching and instruction caching. The analysis can handle a unified cache as well as separate caches for data and instructions
Keywords :
cache storage; parallel programming; pipeline processing; real-time systems; software performance evaluation; caching behaviour; data caching; general case analysis techniques; hard real time programs; instruction caching; instruction level timing analysis; pipelining; processing time improvement; speed up mechanisms; superscalar processors; unified cache; very simple structure; Data analysis; Electronic mail; Flow graphs; Performance analysis; Pipeline processing; Processor scheduling; Real time systems; Runtime; Systems engineering and theory; Timing;
Conference_Titel :
Real-Time Systems, 1997. Proceedings., Ninth Euromicro Workshop on
Conference_Location :
Toledo
Print_ISBN :
0-8186-8034-2
DOI :
10.1109/EMWRTS.1997.613767
