DocumentCode :
3133047
Title :
Multiple tests for each gate delay fault: higher coverage and lower test application cost
Author :
Irajpour, Shahdad ; Gupta, Sandeep K. ; Breuer, Melvin A.
Author_Institution :
Dept. of EE - Syst., Southern California Univ., Los Angeles, CA
fYear :
2005
fDate :
8-8 Nov. 2005
Lastpage :
1219
Abstract :
Different tests for a single gate delay fault can detect different ranges of delay fault sizes. It is of interests to determine whether, for most faults, a single test covers all the ranges of delay fault sizes covered collectively by all tests for the fault. Using an enhanced gate delay fault simulation algorithm, we show that for a considerable number of gate delay faults in benchmark circuits, multiple tests collectively provide more comprehensive coverage than any single test. We then present many key implications of this observation, especially in the areas of test generation and test set compaction
Keywords :
delays; fault simulation; integrated circuit testing; benchmark circuits; delay fault sizes; multiple tests; simulation algorithm; single gate delay fault; test generation; test set compaction; Circuit faults; Circuit simulation; Circuit testing; Compaction; Costs; Delay lines; Electrical fault detection; Fault detection; Semiconductor device testing; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9038-5
Type :
conf
DOI :
10.1109/TEST.2005.1584089
Filename :
1584089
Link To Document :
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