Title :
A GaAs IEEE floating point standard single precision multiplier
Author :
Cui, S. ; Burgess, N. ; Liebelt, M. ; Eshraghian, K.
Author_Institution :
Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
Abstract :
This paper presents a GaAs IEEE floating point standard single precision multiplier. A modified carry save array is used in conjunction with Booth´s algorithm to reduce the partial product addition and interconnection. A special rounding technique called Trailing-1´s Predictor is used to speed up the final addition and rounding. The combination of the fast arithmetic architecture and compact layout style achieves 4 ns multiplication time with 3.5 W power dissipation at 75°C giving 14 mW/MHz. The area is 2.43 mm by 3.77 mm (excluding pads) and uses 28,000 transistors to give a density of 3056 transistors/mm2 for 0.8-μm GaAs technology
Keywords :
III-V semiconductors; digital arithmetic; gallium arsenide; multiplying circuits; 0.8 micron; 3.5 W; 4 ns; 75 degC; Booth´s algorithm; GaAs IEEE floating point standard single precision multiplier; Trailing-1´s Predictor; carry save array; compact layout style; fast arithmetic architecture; interconnection; partial product addition; rounding technique; Australia; Computer architecture; Computer graphics; Delay; Digital arithmetic; Digital signal processing; Gallium arsenide; Integrated circuit interconnections; Signal processing algorithms; Very large scale integration;
Conference_Titel :
Computer Arithmetic, 1995., Proceedings of the 12th Symposium on
Conference_Location :
Bath
Print_ISBN :
0-8186-7089-4
DOI :
10.1109/ARITH.1995.465372
