• DocumentCode
    3133136
  • Title

    A new probing technique for high-speed/high-density printed circuit boards

  • Author

    Parker, Kenneth P.

  • Author_Institution
    Agilent Technol.
  • fYear
    2005
  • fDate
    8-8 Nov. 2005
  • Lastpage
    1261
  • Abstract
    Bullock, in 1987 [Bull87] provided design-for-test (DFT) rules for probing printed circuit boards for in-circuit testing. Many of these rules stand in good stead even today. However, recent technical advances in operational board speed are leading some to believe that in-circuit testing cannot be performed on the high-speed sectors of boards soon to be designed. Due to the increasing usage of high-speed circuitry, there is worry in our industry that in-circuit testing will be marginalized with no good substitute available. It is the purpose of this paper to show how access can be maintained, even on highly dense gigabit logic boards
  • Keywords
    design for testability; high-speed integrated circuits; logic circuits; logic testing; printed circuit testing; design-for-test rules; gigabit logic boards; high-speed circuitry; in-circuit testing; operational board speed; printed circuit boards; probing technique; Circuit testing; Design for testability; Electronic equipment testing; Fixtures; Logic testing; Performance evaluation; Pins; Printed circuits; Probes; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2005. Proceedings. ITC 2005. IEEE International
  • Conference_Location
    Austin, TX
  • Print_ISBN
    0-7803-9038-5
  • Type

    conf

  • DOI
    10.1109/TEST.2005.1584094
  • Filename
    1584094