Title :
Is the concern for soft-error overblown?
Author :
Galivanche, Rajesh
Keywords :
Aging; Circuit synthesis; Costs; Coupling circuits; Logic; Nanoscale devices; Process design; Semiconductor device manufacture; Silicon; Virtual manufacturing;
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Print_ISBN :
0-7803-9038-5
DOI :
10.1109/TEST.2005.1584101
