Reducing random-dopant fluctuation impact on core-speed and power variability in many-core platforms

In this paper, we propose a novel technique that uses multi-Vt design to reduce the impact of random process variation on delay and power in a many-core platform. Random variation is mostly attributed to the random-dopant fluctuation. The proposed technique reduces this fluctuation by lowering the dopant density and then compensating the threshold voltage using a footer transistor. The results show a reduction of the total standard deviation from 25% down to 17% using the proposed method.